HMC704LP4E【PDF 5/44 页】IC FRACT-N PLL 16BIT 24QFN

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Sheet目录1996

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HMC704LP4E

v03.1211

8 GHz fractionaL-n PLL

For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824

Phone: 978-250-3343

Fax: 978-250-3373

Order On-line at www.hittite.com

Application Support: Phone: 978-250-3343 or apps@hittite.com

theory of operation

The PLL consists of the following functional blocks:

Reference Path Input Buffer and ’R’ Divider

2. VCO Path Input Buffer, RF Divide-by-2 and Multi-Modulus ’N’ Divider

3. Δ

Σ Fractional Modulator

4. Phase Detector

5. Charge Pump

6. Main serial Port

Lock Detect and Register Control

8. Auxiliary Output serial Port

9. Power On Reset Circuit

External Vco

The PLL charge pump can operate with the charge pump supply as high as 5.2 Volts. The charge pump output at the

varactor tuning port, normally can maintain low noise performance to within 500mV of ground or 800mV of the upper

supply voltage.

High Performance Low Spurious operation

The HMC704LP4E has been designed for the best phase noise and low spurious content possible in an integrated PLL.

spurious signals in a PLL can occur in any mode of operation and can come from a number of sources.

figure of Merit noise floor and flicker noise Models

The phase noise of an ideal phase locked oscillator is dependent upon a number of factors:

a. Frequency of the VCO, and the Phase detector

b. VCO sensitivity, kvco, VCO and Reference Oscillator phase noise profiles

c. Charge Pump current, Loop Filter and Loop Bandwidth

d. Mode of Operation: Integer, Fractional modulator style

The contributions of the PLL to the output phase noise can be characterized in terms of a Figure of Merit (FOM) for both

the PLL noise floor and the PLL flicker (1/f) noise regions, as follows:

Figure 23. Synthesizer with External VCO

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